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Silicon-based microelectronics are limited to ∼150°C and therefore not suitable for the extremely high temperatures in aerospace, energy, and space applications. While wide-band-gap semiconductors can provide high-temperature logic, nonvolatile memory devices at high temperatures have been challenging. In this work, we develop a nonvolatile electrochemical memory cell that stores and retains analog and digital information at temperatures as high as 600°C. Through correlative scanning transmission electron microscopy, we show that this high-temperature information retention is a result of composition phase separation between the oxidized and reduced forms of amorphous tantalum oxide. This result demonstrates a memory concept that is resilient at extreme temperatures and reveals phase separation as the principal mechanism that enables nonvolatile information storage in these electrochemical memory cells. 

Interface resistance has become a significant bottleneck for solid-state batteries (SSBs). Most studies of interface resistance have focused on extrinsic mechanisms such as interface reactions and imperfect contact between electrodes and solid electrolytes. Interface potentials are an important intrinsic mechanism that is often ignored. Here, we highlight Kelvin probe force microscopy (KPFM) as a tool to image the local potential at interfaces inside SSBs, examining the existing literature and discussing challenges in interpretation. Drawing analogies with electron transport in metal/semiconductor interfaces, we showcase a formalism that predicts intrinsic ionic resistance based on the properties of the contacting phases, and we emphasize that future battery designs should start from material pairs with low intrinsic resistance. We conclude by outlining future directions in the study of interface potentials through both theory and experiment. 

Neuromorphic computers could overcome efficiency bottlenecks inherent to conventional computing through parallel programming and readout of artificial neural network weights in a crossbar memory array. However, selective and linear weight updates and <10-nanoampere read currents are required for learning that surpasses conventional computing efficiency. We introduce an ionic floating-gate memory array based on a polymer redox transistor connected to a conductive-bridge memory (CBM). Selective and linear programming of a redox transistor array is executed in parallel by overcoming the bridging threshold voltage of the CBMs. Synaptic weight readout with currents <10 nanoamperes is achieved by diluting the conductive polymer with an insulator to decrease the conductance. The redox transistors endure >1 billion write-read operations and support >1-megahertz write-read frequencies.